Emulation to me implies simulation, which isn't what an FPGA does.
A configured FPGA and an ASIC are both real electric circuits. In an FPGA the building blocks are larger groups of transistors (typically forming "Look Up Tables") that are connected together by a network of a bajillion electronic switches (read: other transistors). In an ASIC the building block is generally a transistor (although technically any structure you can "tape-out" with lithography) and everything is wired up directly.
Porting this to an ASIC is more gated by access to proprietary tooling than anything else. There's a number of open source efforts to replicate this tooling on older process nodes (search for SkyWater PDK and OpenROAD).
As for how significant this particular RISC-V chip is, there are a bunch of open source RISC-V chips cropping up. This one does seem to have more extensions implemented than the typical RISC-V chip, which is notable. Personally I'm more interested in RISC-V CPUs written in newer tooling (i.e. nMigen or Chisel) rather than Verilog as I find Verilog a trusty but a bit archaic (similar to how C is seen these days).
Emulation just means running it on hardware it wasn't intended. That runs the spectrum between ISA emulators like Dolphin, software RTL simulators like verilator, and FPGAs can certainly be used for emulation if the design wasn't really intended for them as the real end goal.
There's also an interesting point in that spectrum of the cadence/synopsys hardware emulators. They run in a rack sized device composed of a bunch of FPGAs and arrays of custom ascetic processor cores that can only do logic and branch ops to run HDL for SoC sized designs at ~1-10MHz.
A configured FPGA and an ASIC are both real electric circuits. In an FPGA the building blocks are larger groups of transistors (typically forming "Look Up Tables") that are connected together by a network of a bajillion electronic switches (read: other transistors). In an ASIC the building block is generally a transistor (although technically any structure you can "tape-out" with lithography) and everything is wired up directly.
Porting this to an ASIC is more gated by access to proprietary tooling than anything else. There's a number of open source efforts to replicate this tooling on older process nodes (search for SkyWater PDK and OpenROAD).
As for how significant this particular RISC-V chip is, there are a bunch of open source RISC-V chips cropping up. This one does seem to have more extensions implemented than the typical RISC-V chip, which is notable. Personally I'm more interested in RISC-V CPUs written in newer tooling (i.e. nMigen or Chisel) rather than Verilog as I find Verilog a trusty but a bit archaic (similar to how C is seen these days).